GLOSSARY

A

ACC routines
utility routines provided to access simulation data within a model from a user-provided C routine.

always block
a procedural block which loops continuously.

ambiguous signal strength
a signal with multiple strength levels.

assertion check
a bit of Verilog code which checks for a logical condition which should always be true (or false).

ambiguous signal strength
a signal with multiple strength levels.

asynchronous
events or processes which are not ordered with respect to each other.

B

bi-directional primitive
one of tran, rtran, tranif, and rtranif.

bit-select
an operator which produces a single bit from a vector.

blocking assignment
a procedural assignment. This is the normal assignment statement with no special timing characteristics.

breakpoint
a specified point in model execution at which execution should stop. Breakpoints may be specified by time, event, or execution of a particular statement.

C

call routine
a user-provided routine which is called when the user-defined system task or function is executed.

calling reason
a parameter given to a user-provided routine at the time of call to indicate why it is being called.

case statement
a selection statement which executes one of a set of statements, based on the value of a case selector.

casex statement
a variation of case which allows x or z bits in the selector or the case expression to be ignored.

casez statement
a variation of case which allows z bits in the selector or the case expression to be ignored.

check routine
a user-provided routine which is called when the user-defined system task or function is compiled.

checkpoint
a snap-shot of the execution image of a model at a given point in time. Checkpoints are done so that simulation may be resumed from the checkpoint at a later time.

child module
a module which is instantiated by another (parent) module.

CLI
command line interface. Each simulator has its own CLI, often with different command languages.

clock
a periodic signal used to synchronize logic. Clocks are not special signals in Verilog models, but are just ordinary nets or registers whose values change regularly.

combinational UDP
a user-defined primitive whose output is a state-less function of its input ports.

compilation
the process of tranforming the Verilog source statements of a model into an executable (or interpretable) image.

compiler
the program which transforms the model's Verilog source into an executable image, usually an object file.

concatenation
an operation which creates a vector whose width is the sum of its operands' widths.

concurrent
events or processes which may occur or progress at the same time.

consistency check
see assertion check.

continuous assignment
an assignment in declarative code. Continuous assignments are introduced by the assign keyword. The right-hand side expression of the continuous assignment is evaluated as a result of propagation of its operands.

cross-module reference
a reference to a net, register, task or function in another module instance. This is also known as a hierarchical reference. Abbreviated XMR.

D

data event
the event which denotes one end-point of a timing check interval. The other event is the reference event.

deassign
the statement which disables, or releases, a procedural continuous assignment.

declarative code
Verilog statements which are executed as a result of signal propagation. Continuous assignments, primitive, and module instances are declarative.

declared event
an event variable which can be set under program control.

default nettype
the net type used for implicitly defined nets. This is set with the `default_nettype compiler directive.

defparam
a statement that assigns a non-default value to a parameter for a given module instance.

delay
a construct which indicates the passage of simulation time between two events. Delays may occur in procedural code or declarative code.

delay expression
an expression whose value is used for a time delay.

design entry
the process of creating the Verilog source representation of a model. Design entry can be accomplished by either writing source statements using a text editor, or by using a special-purpose program which converts drawn symbols into Verilog source.

disable statement
statement used to stop execution of a task or named block.

distributed delay
a delay attached to a primitive, continuous assignment, or procedural code. Distributed delays are so-called because a path from an input to an output may contain many such delays, the sum of which make up the overall delay.

driver
a model component which can cause a new value to be put onto a net. Drivers can be output ports of module and primitive instances, or continuous assignments.

E

edge event
event which occurs on the rising or falling edge of a signal. There are two edge events: posedge and negedge.

edge-sensitive module path
a module path which begins with an edge transition (posedge or negedge).

edge-sensitive sequential UDP
a sequential user-defined primitive which changes state (and output value) based on input port transitions.

emacs-mode
an addition to the Emacs editor which enables context-sensitive text entry.

error limit
a time value which delimits an error interval for timing checks. If the data event occurs before (or after) the error limit (depending on the particular timing check), then an error is signaled.

escaped identifier
an identifier which is preceded by a \ (backslash). Such an identifier may contain any character in its name,which is terminated only by the next white space.

event
an action or set of actions which take place at a single point in simulated time.

event control
an event which must occur before execution can proceed to the next statement. The statement which follows the event control is the "controlled" statement.

event expression
an expression which may be in an event control. The only operator allowed in an event expression is event or.

event or operator
the operator used in event expressions to make a compound event.

explicit finite-state machine
code which implements a finite-state machine using a separate state transition function and state variable. Explicit state machine code is usually implemented using a case statement.

F

finite-state machine
sequential logic, usually implemented with a case construct.

for statement
a general looping statement, similar to the for statement in C.

force statement
the strongest procedural continuous assign. Deactivated by a corresponding release statement.

forever statement
a special case of a looping statement which does not terminate.

format string
a specification of how output should be printed.

function
a set of procedural statements whose execution results in a single value. Functions may be used as operands in any expression.

G

H

hierarchical reference
a fully-qualified name which uniquely identifies an entity in a model. This is another name for a cross-module reference.

hierarchy
a tree structure of module instances which starts at a top-level module and proceeds to leaf modules.

I

if statement
the standard conditional statement.

implicit finite-state machine
code which implements a finite-state machine using a sequence of procedural statements with time or event controls to manage the timing.

implicit net
a net which is used in a port expression in a module instance without a previous declaration. It will be defined using the default nettype.

incremental compilation
the process of compiling a model in which only the parts of the model which have been changed are transformed, being merged with the already transformed parts which did not change. This is a problematic capability in Verilog.

implicit net
a net which is used in a port expression in a module instance without a previous declaration. It will be defined using the default nettype.

inertial delay
a model of signal propagation through devices which have delays in which a pulse shorter than the delay does not appear on the output. This is the delay model used in Verilog, and it applies to all declarative code delays, including continuous assignments.

initial block
a procedural block which executes only once.

inout port
a bi-directional port.

input port
a port where signal values go from parent to child module.

instance
an embodiment of a module in the overall Verilog model.

instantiation
the statement which creates a module instance.

integer
a type of register. Integers are signed, 32-bit quantities.

interpreter
a program which simulates a Verilog model by re-analyzing each statement or operation as it is executed. Many Verilog simulators are interpreters.

intra-assignment delay
a time delay placed in the middle of an assignment. This causes the right-hand side to be evaluated immediately, but the assignment is not done until after the delay has expired.

intra-assignment event control
an event delay placed in the middle of an assignment. This causes the right-hand side to be evaluated immediately, but the assignment is not done until after the event has occured.

J

K

L

latch inferencing
the process of inserting a latch (or register) into a synthesized netlist to realize the logic described by RTL (or behavioral) code.

level-sensitive event control
an event control which is satisfied when the argument expression becomes true. The expression is re-evaluated whenever any of its operands changes.

library directory
a directory which contains modules for use in Verilog models. Each file in a library directory contains just one module, and the file name indicates the module name contained in it.

library file
a file which contains modules for use in Verilog models. A model which references a library file will have only those modules it references included in the model's execution.

linking
the process of producing an executable image for simulation, including user-provided routines along with the standard simulation library and support routines.

M

macro
an identifier which has its definition substituted for it textually during compilation. Also called a "source macro". Macros are created by the `define statement, and their use is always preceded by ` (back-quote).

Mealy machine
a finite-state machine which produces outputs as a function of both the current state and the input.

memory
an array of registers. The registers may be scalars or vectors. Memories are singly-dimensioned.

misc routine
a user-provided routine which is called when some event occurs which has been enabled by that routine or some other user-provided routine.

model
the logic design that a set of Verilog source files describes. This is a generic term which comes from "simulation model". System and design are often used as synonyms.

module
a logical component of a model. Modules have definitions and instances. The definition contains declarative and procedural code sections, net and register declarations, task and function definitions, module instantiations, and port definitions for connecting to other parts of the hierarchy.

module path
a relationship between a change on an input port and the corresponding change on an output port. The input port-output port pair is considered the path. The path may be further qualified by particular values on the input or output.

module path delay
the delay associated with a module path. A module path delay is a lumped delay (all of the delay is represented in a single "lump" value), as opposed to distributed delays.

Moore machine
a finite-state machine which produces outputs as a function of only the current state.

MOS primitive
one of cmos, rcmos, pmos, rpmos, nmos, or rnmos.

multi-channel descriptor
an integer which is a bit-map to the set of open files for output.

N

named block
a sequential or parallel compound statement which has a label attached. Named blocks may have local variables (registers) declared within them, and may be disabled.

negedge
an edge event which occurs when a transition is made from 1, x, or z to 0.

net
an identifier which has a value determined by its drivers. A net may have more than one driver, and zero or more drivers may be active at any given time.

net driver
a declarative construct (continuous assignment, primitive output port, or module instance output port) which causes a value to be placed onto a net.

netlist
a model which contains only module or primitive instantiations.

non-blocking assignment
an assignment which occurs in two parts, the evaluation part and the update part. The evaluation takes place immediately, but the update is deferred until the end of the time step after all other types of events have occured.

notifier
a register which is toggled in the event of a timing check error.

O

one-hot state encoding
a method of assigning state variable values to states in which only one bit in the state variable is on in any state. For example, three states would have the state values 3'b001, 3'b010, and 3'b100.

output port
a port where signal values go from child module to parent.

P

parallel block
a compound statement in which each statement is executed at the same time (in parallel). Parallel blocks are enclosed by fork...join.

parameter
a run-time constant whose value is determined at compile time. Parameters are useful to change the behavior or structure of different instances of a module.

parent module
a module which instantiates other modules. The instantiated modules are children of this parent.

part-select
an operator which produces a set of contiguous bits from a vector.

path pulse specparam
a parameter which is used to regulate the propagation of pulses through modules with delays. In general, by using a path pulse parameter, you can prevent short pulses from causing further activity on the output of a module path.

pipeline
a set of storage elements (stages) in which the value from each stage is stored in the next stage. Pipelines are usually synchronous, and there may be transformations on the data values between stages (corresponding to combinational logic).

PLI
Programming Language Interface.

pli.tab
a table used by VCS to indicate to the compiler information about user-provided routines, user-provided system tasks and functions, and how they should be related.

port
a connection from the outside into a module (an input port) or a connection from a module to the outside (an output port) or a bi-directional connection (an inout port).

port expression
an expression which appears in a port list, either in an instance (the common case) or a definition (the rare case).

port type
the direction of the port (input, output, or inout).

posedge
an edge event which occurs when a transition is made from 0, x, or z to 1.

primitive
a built-in module type. A primitives may be instantiated like any other module, but its definition is pre-determined.

procedural block
a (compound) statement which makes up a process. The initial and always keywords introduce procedural blocks.

procedural code
statements which appear inside initial or always blocks, or inside tasks or functions.

procedural continuous assign
a continuous assignment which can be activated in procedural code. Deactivated with a deassign statement. Also known as a quasi-continuous assign (QCA).

process
a set of events which are sequential with respect to each other. Typically, an initial or always block is a process.

program counter
a "pointer" to the next statement to be executed in a sequential block. There is one program counter for each process in the simulation model.

propagation
the action of causing declarative code to be executed as the result of a signal (register or net) changing value.

Q

QCA
abbreviation for quasi-continuous assign.

quasi-continuous assign
see procedural continuous assign.

R

race condition
two or more processes which are unordered with respect to each other (or partially ordered) and whose results differ depending on execution order. Race conditions are usually present when a single signal (register or net) is modified in one process and sampled from a different process at the same time.

range
the width specification of a vector. The range is in the form of [high-order-bit:low-order-bit].

real
a floating-point quantity, 64-bit IEEE format.

reference event
the event which denotes one end-point of a timing check interval. The other event is the data event.

register
an identifier which holds a value. Registers are assigned their values in procedural code.

reject limit
time value which sets a minimum length for a pulse. Any pulse less than this limit will not propagate to the output, but will be ignored.

release statement
the statement which deactivates a force.

repeat concatenate
an operation which creates a vector by repeating its operands multiple times.

repeat statement
a specialized looping statement which causes the loop body to be executed a given number of times.

S

scalar
a single-bit quantity. Both nets and registers may be scalars.

sequential block
a compound statement in which each statement is executed in order. Sequential blocks are enclosed by begin...end.

sequential UDP
a user-defined primitive whose output is a function of both its input ports and its previous output, or state.

simple module path
a module path whose source is an input port, or bit- or part-select of an input port, or a list of input ports, or bit- or part-selects. The destination is an output port or bit- or part-select of an output port, or a list of them.

simulation
the execution of a model to reveal its behavior.

simulation history
a trace of the simulation behavior. A simulation history is usually contained in a dumpfile, and produced by the $dumpvars system task or a varient of it.

simulation time
the value of the central clock in the simulation.

single-input primitive
a primitive which has only one input port and (potentially) more than one output port. The input port is the last in the list. The single-input primitives are not and buf.

single-output primitive
a primitive which has only one output port and (potentially) more than one input port. The output port is the first in the list. The single-output primitives are and, or, xor, nand, nor, and xnor.

sized constant
a constant whose width is explicitly specified.

sparse memory
a particular application of the PLI.

specify block
section of a module which supplies detailed timing information about the module.

specparam
a specparam is a parameter used in specify blocks. Specparams can be modified through the PLI for back-annotation.

state encoding
the mapping of state variable values to states. For example, if the state variable is 3 bits wide, and there are 4 states (A, B, C, D), a state encoding would be A - 3'b001, B - 3'b010, C - 3'b011, D - 3'b100.

state-dependent path
a module path that is qualified by the value of one or more signals. Thus different paths can have the source and sink by being qualified by different states.

state memory
the location used to hold the state variable.

state variable
the value which indicates the current state of the state machine. This is also sometimes called the state vector.

strength scalar
a scalar whose value may be one of 120 different values. Strengths are mapped into 0, 1, x, or z, and may be combined to form other strength values. For example, a strong 1 combined with a weak 0 will produce a 1 as a result.

switch primitive
a primitive which is intended to model transistor-level structures. The switch primitives are nmos, pmos, cmos, rnmos, rpmos, and rcmos.

system function
a function whose definition is built-in. System functions all begin with "$".

system task
a task whose definition is built-in. System tasks all begin with "$".

T

task
a set of procedural statements which are treated as a sub-unit. Tasks may be invoked from other procedural blocks, including other tasks.

task enable
the act of invoking a task.

TF routines
utility routines provided to access simulation data within a model from a user-provided C routine. These routines primarily deal with nets and registers which appear as arguments to the user-defined system task or function.

time
a 64-bit unsigned register. Time registers are used to hold the simulation time, which is a 64-bit positive number.

time control
a time delay which must occur before execution can proceed to the next statement. The statement which follows the time control is the "controlled" statement.

time scale
the time unit and precision to be applied to delays. This is a means of providing a physical meaning to the otherwise dimensionless time units of simulation.

time unit
the unit for all delays which appear after the `timescale directive.

timing check task
a system task which appears in a specify block. Timing check tasks enforce timing constraints on signal change events.

time precision
the minimum unit of accuracy is for delays in the model.

transport delay
a model of signal propagation through devices which have delays in which a pulse shorter than the delay appears faithfully on the output. This is not the delay model used in Verilog, though it can be realized using the PLI.

transition event
event which occurs on the change of a signal. Edge events are special cases of transition events.

tri-state primitive
a primitive which can produce a z value on its output. The tri-state primitives are bufif1, bufif0, notif1, and notif0.

two-phase clock
a clock made of two signals. The two signals are usually inverses of each other, with an offset so that consecutive latches triggered with different clock phases will have a margin of safety to prevent unwanted flow-through.

U

upward reference
a cross-module reference which is resolved by looking up in the heirarchy to the parent module for resolution. The actual reference target may be found anywhere in the hierarchy except in a descendant of the referencing module instance.

unambiguous signal strength
a signal with a single strength level.

unit-delay model
a model in which all delays have the value 1. Unit delay models are sometimes more efficient to simulate because there are fewer distinct times in which events occur. Their disadvantage is that they do not capture the timing behavior of the design being modelled.

user-defined primitive
a primitive defined by means of a truth table.

V

vector
a multiple-bit quantity. Nets and registers may be vectors. Vectors have only one dimension.

veriuser.c
a C file which contains the veriusertfs table for Verilog-XL.

veriuser.h
a C header file which defines many constants used by PLI routines.

veriusertfs
the table used by Verilog-XL to communicate information about user-provided routines, user-provided system tasks and functions, and how they should be related.

W

wait event control
wait is the keyword which specifies a level-sensitive event control.

waveform
a picture of a signal (net or register) value over time. Waveforms can be produced from simulation history files, or directly from the simulation.

while statement
a looping statement similar to the while statement in C.

X

XL algorithm
a method of handling signal changes which occur before a delay has expired. The XL algorithm is faster to simulate, but less accurate than a strict inertial delay.

XMR
abbrevation for cross-module reference.

Y

Z

zero-delay model
a model in which there are no time delays other than the delays which govern the behavior of the clock. All other delays are derived from clock events.