P37X ISA

The ISA will will implement in CSE 371/372 is called P37X. It is a simple RISC ISA that resembles a combination of MIPS and LC3. The following analogy is roughly true: P37X is to LC3 as MIPS is to x86.

P37X shares the following features with LC3 (and differences with MIPS):

• It is 16 bit, i.e., virtual addresses are assumed to be 16 bits long (MIPS uses 32 bit virtual addresses).
• Instructions are 16 bits long (MIPS instructions are 32 bits long).
• There is only one load/store data size, 16 bits (MIPS supports four load/store data sizes: 8, 16, 32 and 64 bits).
• There are no floating point instructions or registers (MIPS has floating point instructions and 32 32-bit floating point registers).
• There are 8 general purpose 16-bit integer registers (MIPS has 32 32-bit integer registers).
• There are no hardwired register values (In MIPS, register 0 is hardwired to 0).
• It uses register 7 as the implicit return address register for calls and traps (MIPS uses register 31).
• It has a processor status register (PSR) whose most-significant-bit (MSB) encodes the processor's current privelege mode (MIPS has an entire register file of priveleged registers called the coprocessor0 register file).
• It has a memory protection register (MPR) whose bits represent the access privelege (OS priveleged vs. non-priveleged) of all of memory in 4KB chunks (MIPS does not have a memory protection register, it uses virtual memory protection).
• Both ISAs support the same basic memory-mapped I/O devices (keyboard, console output, timer, video display)

• P37X has only two addressing mode, register+displacement and PC+displacement, which are nearly equivalent for implementation purposes (LC3 also has a memory-indirect addressing mode).
• P37X has a full complement of arithmetic, logical, and shift operations (LC3 only has AND, NOT, and ADD).
• P37X's conditional branch instructions perform comparisons on an explicit register (LC3 uses condition codes).

Machine Instructions

The following table contains the P37X machine instructions, the ones the hardware can execute directly.

The P37X assembler is of course symbolic, and it allows you to specify PC offsets as symbolic label references rather than numeric constants. A label can (optionally) prepend every instruction or be on a line by itself. A label is a string consisting of letters, digits, and underscores, e.g., FOO, FOO0, or _FOO_0:. A label cannot begin with a digit. This is similar to the LC3 assembler. Notice, that in P37X all PC-relative instructions are actually relative to PC+1.

Memory-Mapped I/O Devices

The P37X has several memory-mapped I/O devices and control registers:

Input:

• Keyboard: Keyboard status register (KSR) is 0xFE00; Keyboard data register (KDR) is 0xFE02.
• Extention board switches: TBD
• Timer: Timer register (TMR) is 0xFE08; Timer interval register (sets the length of timer delay) is 0xFE0A.

Output:

• Video display: A 128 column by 120 row video display. Each pixel is the lower 15-bits of a word (5-bit red, 5-bit green, 5-bit blue). The starting address is 0xC000; Note: the LC-3 was 128x124, so the P37X's display isn't quite a big.
• Eight LEDs: TBD
• Seven-segment display: TBD

Control:

• Memory protection register (MPR) is 0xFE12;

Static Data and Assembler Directives

Like the LC3 assembler, the P37X assembler supports static data declarations and a number of other assembler directives. An assembler directive is different than an instruction or even a pseudo-instruction in that it doesn't actually correspond to any instruction execution at runtime. P37X uses the same exact directives as LC3, and they all start with a period. Directives can also be labeled.

In case you forgot, the following table summarizes the P37X (LC3) directives.

"OS" Trap Routines

P37X also supports all of LC3's trap codes and the associated "OS" routines, although it sometimes gives them different mnemonic names. It also implements them in a different way. In LC3, the trap-vector is a vector of addresses and the TRAP instruction saves the return address, changes privilege mode, dereferences this vector at the proper position, and jumps to the dereferenced address. Basically an LC3 TRAP does a load and a call in one instruction.

Since such a compound operation would be complex to implement in hardware, P37X TRAP instructions work differently. A P37X TRAP saves the return address, changes the privilege mode, and jumps to the trap-vector. The trap-vector itself contains not the address of the routine, but an instruction that jumps to that address. Instead of doing a load and a call in one instruction, P37X implements traps by doing a call (the TRAP) and a jump in two instructions.

At this point you may be wondering "Why doesn't LC3 implement traps using separate load and call instructions?" The answer has to do with the fact that a call actually performs two steps: i) it saves the return address (link), and ii) jumps to the target address. In an LC3 TRAP, these two steps have to take place on either side of the load: the link has to happen before the load, the jump has to happen after.

Anyway, implementation aside, the traps work the same from the programmer's perspective. In case you forgot, the following table summarizes the P37X (LC3) trap codes and routines.