Publications

The journal and conference publications are all copyrighted by ACM or IEEE. Please respect these copyrights and do not distribute copies for any commercial purpose.

2022

OCOLOS: Online COde Layout OptimizationS
Yuxuan Zhang, Tanvir Ahmed Khan, Gilles Pokam, Baris Kasikci, Heiner Litz and Joseph Devietti
ACM IEEE International Symposium on Microarchitecture (MICRO '22), October 2022

2021

Twig: Profile-Guided BTB Prefetching for Data Center Applications
Tanvir Ahmed Khan, Nathan Brown, Akshitha Sriraman, Niranjan K Soundararajan, Rakesh Kumar, Joseph Devietti, Sreenivas Subramoney, Gilles Pokam, Heiner Litz and Baris Kasikci
ACM IEEE International Symposium on Microarchitecture (MICRO '21), October 2021

Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications
Tanvir Ahmed Khan, Dexin Zhang, Akshitha Sriraman, Joseph Devietti, Gilles Pokam, Heiner Litz and Baris Kasikci
International Symposium on Computer Architecture (ISCA '21), June 2021

2020

I-SPY: Context-Driven Conditional Instruction Prefetching with Coalescing
Tanvir Ahmed Khan, Akshitha Sriraman, Joseph Devietti, Gilles Pokam, Heiner Litz and Baris Kasikci
ACM IEEE International Symposium on Microarchitecture (MICRO '20), October 2020

Deterministic Atomic Buffering
Yuan Hsi Chou, Christopher Ng, Shaylin Cattell, Jeremy Intan, Matthew Sinclair, Joseph Devietti, Timothy G. Rogers and Tor Aamodt
ACM IEEE International Symposium on Microarchitecture (MICRO '20), October 2020

Reproducible Containers
Omar Navarro Leija, Kelly Shiptoski, Ryan Scott, Baojun Wang, Nicholas Renner, Ryan Newton and Joseph Devietti
International Conference on Architectural Support for Programming Languages & Operating Systems (ASPLOS '20), March 2020

Hurdle: Securing Jump Instructions Against Code Reuse Attacks
Christian DeLozier, Kavya Lakshminarayanan, Gilles Pokam and Joseph Devietti
International Conference on Architectural Support for Programming Languages & Operating Systems (ASPLOS '20), March 2020

2019

Lazy Determinism for Faster Deterministic Multithreading
Timothy Merrifield, Sepideh Roghanchi, Joseph Devietti and Jakob Eriksson
International Conference on Architectural Support for Programming Languages & Operating Systems (ASPLOS '19), April 2019

2018

Block-Size Independence for GPU Programs
Rajeev Alur, Joseph Devietti and Nimit Singhania
Static Analysis Symposium (SAS '18), August 2018
Radhia Cousot Young Researcher Best Paper Award

CURD: A Dynamic CUDA Race Detector
Yuanfeng Peng, Vinod Grover and Joseph Devietti
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '18), June 2018

SlimFast: Reducing Metadata Redundancy in Sound and Complete Dynamic Data Race Detection.
Yuanfeng Peng, Christian DeLozier, Ariel Eizenberg, William Mansky and Joseph Devietti
IEEE International Parallel & Distributed Processing Symposium (IPDPS '18).

SOFRITAS: Serializable Ordering-Free Regions for Increasing Thread Atomicity Scalably.
Christian DeLozier, Ariel Eizenberg, Brandon Lucia, Joseph Devietti.
ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '18).

2017

A Monad for Deterministic Parallel Batch Processing.
Ryan Scott, Omar Navarro Leija, Joseph Devietti and Ryan Newton.
ACM SIGPLAN International Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA '17), October 2017

PARSNIP: Performant Architecture for Race Safety with No Impact on Precision.
Yuanfeng Peng, Ben Wood and Joseph Devietti.
ACM IEEE International Symposium on Microarchitecture (MICRO '17), October 2017.

TMI: Thread Memory Isolation for False Sharing Repair.
Christian DeLozier, Ariel Eizenberg, Shiliang Hu, Gilles Pokam and Joseph Devietti.
ACM IEEE International Symposium on Microarchitecture (MICRO '17), October 2017.

GPUDrano: Detecting Uncoalesced Accesses in GPU Programs.
Rajeev Alur, Joseph Devietti, Omar Navarro Leija and Nimit Singhania.
International Conference on Computer-Aided Verification (CAV '17), July 2017.

BARRACUDA: Binary-level Analysis of Runtime RAces in CUDA programs.
Ariel Eizenberg, Yuanfeng Peng, Toma Pigli, William Mansky and Joseph Devietti.
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '17), June 2017.

Verifying Dynamic Race Detection.
William Mansky, Yuanfeng Peng, Steve Zdancewic and Joseph Devietti.
Certified Programs and Proofs (CPP '17), co-located with POPL 2017, January 2017.

2016

Remix: Online Detection and Repair of Cache Contention for the JVM.
Ariel Eizenberg, Shiliang Hu, Gilles Pokam and Joseph Devietti.
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '16), June 2016.

LASER: Light, Accurate Sharing dEtection and Repair.
Liang Luo, Akshitha Sriraman, Brooke Fugate, Shiliang Hu, Gilles Pokam, Chris Newburn and Joseph Devietti.
IEEE International Symposium on High Performance Computer Architecture, March 2016.

2014

MAMA: Mostly Automatic Management of Atomicity.
Christian DeLozier, Joseph Devietti, and Milo Martin.
WoDet, March 2014.

2013

Ironclad C++: A Library-Augmented Type-Safe Subset of C++.
Christian DeLozier, Richard Eisenberg, Santosh Nagarakatte, Peter-Michael Osera, Milo M. K. Martin, and Steve Zdancewic.
OOPSLA, October 2013. (slides)

Computational Sprinting on a Hardware/Software Testbed
Arun Raghavan, Laurel Emurian, Lei Shao, Marios Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch and Milo M. K. Martin
ASPLOS, March 2013.

2012

Multicore Acceleration of Priority-based Schedulers for Concurrency Bug Detection.
Santosh Nagarakatte, Sebastian Burckhardt, Milo M K Martin and Madan Musuvathi
PLDI, June 2012.

Watchdog: Hardware for Safe and Secure Manual Memory Management and Full Memory Safety.
Santosh Nagarakatte, Milo M K Martin and Steve Zdancewic
ISCA, June 2012.

Computational Sprinting
Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch and Milo M. K. Martin
HPCA, February 2012.
(Slides)

Formalizing LLVM Intermediate Representation for Verified Program Transformations
Jianzhou Zhao, Santosh Nagarakatte, Milo M K Martin and Steve Zdancewic
POPL, January 2012.

2010

Token Tenure and PATCH: A Predictive/Adaptive Token Counting Hybrid
Arun Raghavan, Colin Blundell and Milo M K Martin
TACO, September 2010.

RetCon: Transactional Repair without Replay
Colin Blundell, Arun Raghavan, and Milo M K Martin
ISCA, June 2010.

CETS: Compiler Enforced Temporal Safety for C
Santosh Nagarakatte, Jianzhou Zhao, Milo M K Martin and Steve Zdancewic
ISMM, June 2010.

Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically
Matthew Hicks, Murph Finnicum, Samuel T King, Milo M K Martin and Jonathan M Smith
31st IEEE Symposium on Security and Privacy, May 2010.

SMT-Directory: Efficient Load-Load Ordering for SMT
Andrew Hilton and Amir Roth
IEEE Computer Architecture Letters, Vol 12, May 2010.

BOLT: Energy-Efficient Out-of-Order Latency-Tolerant Execution
Andrew Hilton and Amir Roth
HPCA, Feb 2010.

iCFP: Tolerating All Level Cache Misses in In-Order Processors
Andrew Hilton, Santosh Nagarakatte, and Amir Roth
IEEE MICRO, Vol 30, No. 1, Jan./Feb., 2010.

2009

Decoupled Store Completion/Silent Deterministic Replay: Enabling Scalable Data Memory for CPR/CFP Processors.
Andrew Hilton and Amir Roth
ISCA, June 2009.

INVISIFENCE: Performance-Transparent Memory Ordering in Conventional Multiprocessors.
Colin Blundell, Milo M. K. Martin and Thomas F. Wenisch
ISCA, June 2009.

SoftBound: Highly Compatible and Complete Spatial Memory Safety for C.
Santosh Nagarakatte, Jianzhou Zhao, Milo M. K. Martin and Steve Zdancewic
PLDI, June 2009.

iCFP: Tolerating All Level Cache Misses in In-Order Processors.
Andrew Hilton, Santosh Nagarakatte, and Amir Roth
HPCA, February 2009.

2008

Token Tenure: PATCHing Token Counting Using Directory-Based Cache Coherence.
Arun Raghavan, Colin Blundell, and Milo M. K. Martin
MICRO, November 2008.

HardBound: Architectural Support for Spatial Safety of the C Programming Language.
Joe Devietti, Colin Blundell, Milo M. K. Martin, and Steve Zdancewic
ASPLOS, March 2008.

2007

Making the Fast Case Common and the Uncommon Case Simple in Unbounded Transactional Memory.
Colin Blundell, Joe Devietti, E Christopher Lewis, and Milo M. K. Martin
ISCA-34, June 2007.
Talk: 4-up pdf, ppt

Ginger: Control Independence Using Tag Rewriting.
Andrew Hilton and Amir Roth
ISCA-34, June 2007.

CheckFence: Checking Consistency of Concurrent Data Types on Relaxed Memory Models.
Sebastian Burckhardt, Rajeev Alur, and Milo M. K. Martin
PLDI, June 2007.

2006

Serialization-Aware Mini-Graphs: Performance with Fewer Resources.
Anne Bracy and Amir Roth
MICRO-39, December 2006.

NoSQ: Store-Load Communication without a Store Queue.
Tingting Sha, Milo M.K. Martin, and Amir Roth
MICRO-39, December 2006.

Subleties of Transactional Memory Atomicity Semantics.
Colin Blundell, E Christopher Lewis, and Milo M. K. Martin
Computer Architecture Letters, Volume 5, Number 2, November 2006.

Store Vulnerability Window (SVW): A Filter and Potential Replacement for Load Re-Execution.
Amir Roth
JILP, Vol. 8, September 2006.

2005

Scalable Store-Load Forwarding via Store Queue Index Prediction.
Tingting Sha, Milo M.K. Martin, and Amir Roth
MICRO-38, November 2005.

Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization.
Amir Roth
ISCA-32, June 2005.

Energy Aspects of Pre-Execution and Energy-Aware P-Thread Selection.
Vlad Petric and Amir Roth
ISCA-32, June 2005.

RENO: A Rename-Based Instruction Optimizer.
Vlad Petric, Tingting Sha, and Amir Roth
ISCA-32, June 2005.

Deconstructing Transactional Semantics: The Subtleties of Atomicity.
Colin Blundell, E Christopher Lewis, and Milo M.K. Martin
Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 2005.
Talk: pdf

Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE.
Marc L. Corliss, E Christopher Lewis, and Amir Roth
HPCA-11, February 2005.
Talk: ppt, 1-up pdf, 4-up pdf

Improving Multiple-CMP Systems Using Token Coherence.
Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, and David A. Wood
International Symposium on High Performance Computer Architecture (HPCA), February 2005.

Verifying Safety of a Token Coherence Implementation by Parametric Compositional Refinement.
Sebastian Burckhardt, Rajeev Alur, and Milo M. K. Martin
Sixth International Conference on Verification, Model Checking and Abstract Interpretation (VMCAI), January 2005.

The Implementation and Evaluation of Dynamic Code Decompression using DISE.
Marc L. Corliss, E Christopher Lewis, and Amir Roth
Transactions on Embedded Computing Systems, February 2005.

2004

Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth.
Anne Bracy, Prashant Prahlad, and Amir Roth
MICRO-37, December 2004.

Using DISE to Protect Return Addresses from Attack.
Marc L. Corliss, E Christopher Lewis, and Amir Roth
WASSA, October 2004.

2003

Token Coherence: A New Framework for Shared-Memory Multiprocessors.
Milo M.K. Martin, Mark D. Hill, and David A. Wood.
IEEE Micro, November-December 2003.

A DISE Implementation of Dynamic Code Decompression.
Marc L. Corliss, E Christopher Lewis, and Amir Roth.
LCTES, June 2003.
Talk: 1-up pdf

DISE: A Programmable Macro Engine for Customizing Applications.
Marc L. Corliss, E Christopher Lewis, and Amir Roth.
ISCA-30, June 2003.
Talk: 1-up pdf, 4-up pdf

2002

Three Extensions to Register Integration.
Vlad Petric, Anne Bracy, and Amir Roth.
MICRO-35, November 2002.

A Quantitative Framework for Automated Pre-Execution Thread Selection.
Amir Roth and Gurindar S. Sohi.
MICRO-35, November 2002.